ADMA is a feature of some PCI ATA controllers, ADMA eliminates the need for the driver to send the READ and WRITE commands to the drive. The Bus Mastering Controller sets up both sides of every DMA transfer, and initiates the transfer itself. All the driver needs to do is set up a table of "commands" (a CPB), set some pointers, and then turn on ADMA mode. This greatly reduces excessive IO operations, and frees up precious CPU time.
An ADMA capable controller maps the standard ATA IO and ADMA registers at a 64-bit or 32-bit address (...PCI BAR 4/5, 20h-27h). The size of this area is 1024 bytes.
ADMA supports Queued and Overlapped ATA command sets, but neither is necessary to support ADMA. Both the ATA and ATAPI commands sets are supported.
Detection and Initialization
The ATA/ATAPI Host Adapters Standard specifies a PCI Class Code, details initialization, and operation of ADMA devices.
126.96.36.199 PCI Class Code / Table 14 – ADMA PCI Class Code
- Programming Interface Code: 20h – Single Stepping / 30h – Continuous Operation
- Sub-class Code: 05h – ATA
- Base-Class Code: 01h – Mass Storage
Several vendors have chosen ADMA mode as the basis for their SATA controller implementations, however, often these implementations contain proprietary extensions. For this reason, the PCI Class may be different... driver "quirks" may be required to support these devices.
- http://www.t13.org/Documents/UploadedDocuments/technical/e00149r0.pdf -- Initial specification
- http://www.t13.org/Documents/UploadedDocuments/project/d1510r1-Host-Adapter.pdf -- Latest draft of "ATA/ATAPI Host Adapters Standard"