Instruction Set Architecture

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This page is intended to provide an explanation of the various instruction set architecture principles such as Complex Instruction Set, Reduced Instruction Set, Writable Instruction Set, Single Instruction Set, etc. The instruction sets are named beginning with the simplest toward the complexest set.
See also Historical Notes on CISC and RISC.


Church-Turing Thesis

For the beginning of theoretical informatics Alan Turing(*1912,✝) was maybe the most important person. The Church-Turing thesis states that any algorithm computable by humans (without time and memory limitaions and of course failure free) is computable by an Church-Turing powerful machine.
To be Church-Turing mighty, it is sufficient to be able to load data, change it in any possible way and store it afterwards. Saving and Storeing a value is selfexplaining, the interesting part is the processing.
Common algorithms:

  • logic functions: One might not notice, but f.e. brains use in daily challenges for decisions simple state machines and every state machine can be expressed by logic functions.
  • comparisions: Is this red brighter than this? Answer: Yes or No. See example above. This is implemented by an addition or rather a substraction. Can be implemented by logical functions.
  • multiplications/divisions: Used f.e. in case of applying weights. Can be implemented by addition and substraction (Think about it!), and addition can be implemented by logic functions, so ...
  • integration/differentiation: Any physic law may be implemented by using integration and differentiation. Can be implemented by multiplication or rather division, and this can be implemented by ...

As you might have noticed everything can be implemented by logic functions. This is important: To be able to do any logic function means to be Church-Turing mighty.

To be exact only (f.e.) the NAND function with two inputs and one output is needed. Other sets of "complete" logic functions can be found, but the most common is the NAND function.

Any Instruction Set Architecture (ISA) is Church-Turing mighty.

Flynn's Bottleneck and Fisher's Optimism

M. J. Flynn (*1934) found 1970 a very interesting fact: If one fetches(loads) only one instruction per cycle, one will never get more than one executed instruction per cycle. (This is valid for each physical ALU.)(Think about it!)
J. A. Fisher (*1946) argued 1984 an array (packed) data structure could achive more executed instructions per cylce than one.
This will become important speaking about RISC/CISC dis-/advantages.

One Instruction Set

The so called Ultimate Reduced Instruction Set Computer (URISC) is programmed by only one instruction. This instruction must be possible however to decide, to move data, to jump to different targets in the instruction stream and to calculate. This is only possible with a complex instruction.
Applications for a computer programmed by this ISA have a huge-sized code, so that this ISA is only of theoretical interest. For further information refer to [1].

Minimal Instruction Set

It is defined by less than 32 instructions (It can't be really distinguished between MIS and RIS.). Mostly MISCs are Stackmachines. Owing to missing security features and the huge code size this ISA is not used anymore, but always a part of more sophisticated ISAs. For further information refer to [2].

Reduced Instruction Set

A RISC provides fast and simple basic instructions, e.g. conditional jumps, logic functions, addition/substraction, multiplication/division, a.s.o. It's execution environment is simple, because RISC must not provide complex instructions. This might cause security issues. Often Flynn's bottleneck applies, because data can't be processed in advanced structures. (ISA must be simple by definition.)

Examples: previous ARM and MIPS generations

Complex Instruction Set

A CISC instantiates simple and additional complex instructions. It comes mostly with different execution environments and security features. Espacially streaming extensions like SSE must be named. They are the reason why RISC-only processors almost disappeared nowadays. Flynn's bottleneck applies, but by useing streaming extensions the chance to reduce its influence and switch to Fisher's optimism grows rapitedly. Other advanced features may reduce memory accesses and therefor idle times of the CPU. Clearly the advantage of the CISC-architecture are its capabilities, but that complexity is a disadvantage as well and can result (by not handle them) in serious security issues.

Example: x86

Hybrid Instruction Set

RISC-processors can be build more easier and clocked faster. Any modern CPU is build uppon a RISC. But one do not want missing the advanced instruction a CISC provides. So a hybrid is build. The RISC is used as ALU and is wrapped by a CISC environment. Any instruction is interpreted by this CISC and is splitted in one or more subcode instructions, so called microopcodes, for the RISC. Additionally the CISC-wrap promise security and operating system stability and contoll. Nowadays only microcontroller are pure RISCs, any other CPU is more or less a hybrid RISC-CISC CPU.

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