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• 16:53, 11 November 2015 Intx13 talk contribs uploaded File:OVMF run app.png
• 15:45, 11 November 2015 Intx13 talk contribs uploaded File:OVMF browse fs.png
• 14:32, 11 November 2015 Intx13 talk contribs uploaded File:OVMF shell.png
• 21:15, 20 February 2013 Intx13 talk contribs uploaded File:Multi-bus-PCI-host-controller-with-multiple-bridges.png (This figure illustrates a system with a PCI host controller that supports two buses, one of which has two bridges. To ensure that the two bridged expansion cards are accessible, a daisy-chain would need to be set up from the PCI host controller (either it)
• 21:04, 20 February 2013 Intx13 talk contribs uploaded File:Correct-flow-of-PCI-traffic.png (This figure illustrates how traffic really flows from the host controller to bridges and the devices they host. Bridges are daisy-chained until there is a single path from the host controller through every bridge.)
• 21:00, 20 February 2013 Intx13 talk contribs uploaded File:Incorrect-flow-of-PCI-traffic.png (Sadly this is NOT how traffic flows from a PCI host controller to devices connected to bridges. However, it simplifies things to start with this figure when introducing bridges.)
• 20:48, 20 February 2013 Intx13 talk contribs uploaded File:PCI-host-controller-and-single-bridge.png (In this illustration, a PCI host controller has three attached devices. One of those devices is a bridge, which has two attached devices. Traffic destined for one of the devices attached to the bridge flows from the host controller to the bridge and then )
• 20:34, 20 February 2013 Intx13 talk contribs uploaded File:PCI-host-controller-in-x86-architecture.png (In the x86 architecture, the PCI host controller is integrated into the Southbridge. The Processor/Northbridge/Southbridge, produced by a single vendor, exposes the PCI host controller (and, by extension, the PCI buses) to software via port-mapped IO, mem)
• 20:28, 20 February 2013 Intx13 talk contribs uploaded File:PCI-host-controller-as-software-interface.png (In modern systems the PCI host controller is often integrated into the CPU and exposes PCI buses to software via some CPU-specific IO mechanism, such as memory-mapped IO. This is in contrast with USB, where the USB host controller is connected to the CPU )
• 20:06, 20 February 2013 Intx13 talk contribs uploaded File:Lspci-with-multifunction-device-highlighted.png (This is the output of the "lspci" command on a Debian installation. The highlighted entries illustrate a multi-function PCI device that uses functions 0 and 1 on bus 0, slot 7. )