The Translation Lookaside Buffer (TLB) is a cache used to speed up virtual address translation.
There are certain instances which will cause the TLB will be flushed. That is, some or all of the entries will be invalidated.
These cases will cause full TLB flush, emptying all pages from the cache:
- modifying the PE or PG flags in CR0
- modifying the PSE, PGE, or PAE flags in CR4
- writing to an MTTR
These cases will cause a partial TLB flush, where everything but global pages are empty:
- any write to CR3
- hardware task switches which change CR3
A single page can be invalidated through the INVLPG instruction