View source for Template:X86 protected mode interrupts

<noinclude>
Originally created for Wikipedia. [https://en.wikipedia.org/w/index.php?title=Template:X86_protected_mode_interrupts&oldid=1283313564]

Copied from: [https://wiki.jwo.cz/wiki/x86_protected_mode_interrupts]

This table contains information collected from the ''Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3 (3A, 3B, 3C & 3D): System Programming Guide'' revision from April&nbsp;2022.

== Interrupt table ==

</noinclude>
{| class="wikitable sortable"
|+ x86 Interrupt descriptor table items<ref>''Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3 (3A, 3B, 3C & 3D): System Programming Guide'', April 2022</ref> <span class="plainlinks" style="font-weight: normal">&#x5b;[https://wiki.osdev.org/Template:x86_protected_mode_interrupts?action=edit edit table]]</span>
|-
! class="unsortable" colspan="2" | {{abbr|Int. №|Interrupt number}}
! rowspan="2" | {{abbr|Mnem.|Mnemonic}}
! rowspan="2" | Type
! rowspan="2" | {{abbr|Err. code|Error code}}
! class="unsortable" rowspan="2" | Name
! class="unsortable" rowspan="2" style="text-align: left" | Source
|-
! class="unsortable" | {{abbr|hex|Hexadecimal}}
! {{abbr|dec|Decimal}}
|-
| 0x00
| 0
| #DE 
| Fault 
| {{no|No}}
| Divide Error 
| DIV and IDIV instructions. 
|-
| 0x01
| 1
| #DB 
| Trap
| {{no|No}}
| Debug Exception 
| Instruction, data, and I/O breakpoints; single-step; and others. 
|-
| 0x02
| 2
| NMI
| Interrupt 
| {{no|No}}
| NMI Interrupt 
| Nonmaskable external interrupt. 
|-
| 0x03
| 3
| #BP 
| Trap 
| {{no|No}}
| Breakpoint 
| INT3 instruction. 
|-
| 0x04
| 4
| #OF 
| Trap 
| {{no|No}}
| Overflow 
| INTO instruction. 
|-
| 0x05
| 5
| #BR 
| Fault 
| {{no|No}}
| BOUND Range Exceeded 
| BOUND instruction. 
|-
| 0x06
| 6
| #UD 
| Fault 
| {{no|No}}
| Invalid Opcode (Undefined Opcode) 
| UD instruction or reserved opcode. 
|-
| 0x07
| 7
| #NM 
| Fault 
| {{no|No}}
| Device Not Available (No Math Coprocessor) 
| Floating-point or WAIT/FWAIT instruction. 
|-
| 0x08
| 8
| #DF 
| Abort 
| {{yes|Yes (zero)}}
| Double Fault 
| Any instruction that can generate an exception, an {{abbr|NMI|Non-maskable interrupt}}, or an {{abbr|INTR|external interrupt}}. 
|-
| 0x09
| 9
| {{na}}
| Fault 
| {{no|No}}
| Coprocessor Segment Overrun (reserved) 
| Floating-point instruction.
|-
| 0x0A
| 10
| #TS 
| Fault 
| {{yes|Yes}}
| Invalid TSS 
| Task switch or TSS access. 
|-
| 0x0B
| 11
| #NP 
| Fault 
| {{yes|Yes}}
| Segment Not Present 
| Loading segment registers or accessing system segments. 
|-
| 0x0C
| 12
| #SS 
| Fault 
| {{yes|Yes}}
| Stack-Segment Fault 
| Stack operations and {{abbr|SS|stack segment}} register loads. 
|-
| 0x0D
| 13
| #GP 
| Fault 
| {{yes|Yes}}
| General Protection 
| Any memory reference and other protection checks. 
|-
| 0x0E
| 14
| #PF 
| Fault 
| {{yes|Yes}}
| Page Fault 
| Any memory reference. 
|-
| 0x0F
| 15
| colspan="2" {{na}}
| {{no|No}}
| colspan="2" {{na|Intel reserved. Do not use.|align=left}}
|-
| 0x10
| 16
| #MF 
| Fault 
| {{no|No}}
| x87 FPU Floating-Point Error (Math Fault) 
| x87 FPU floating-point or WAIT/FWAIT instruction. 
|-
| 0x11
| 17
| #AC 
| Fault 
| {{yes|Yes (zero)}}
| Alignment Check 
| Any data reference in memory.
|-
| 0x12
| 18
| #MC 
| Abort 
| {{no|No}}
| Machine Check 
| Error codes (if any) and source are model dependent. 
|-
| 0x13
| 19
| #XM 
| Fault 
| {{no|No}}
| SIMD Floating-Point Exception 
| SSE/SSE2/SSE3 floating-point instructions
|-
| 0x14
| 20
| #VE 
| Fault 
| {{no|No}}
| Virtualization Exception 
| EPT violations
|-
| 0x15
| 21
| #CP 
| Fault 
| {{yes|Yes}}
| Control Protection Exception 
| RET, IRET, RSTORSSP, and SETSSBSY instructions can generate this exception. When CET indirect branch tracking is enabled, this exception can be generated due to a missing ENDBRANCH instruction at target of an indirect call or jump. 
|-
| 0x16<br>⋮<br>0x1f
| 22<br>⋮<br>31
| colspan="3" {{unknown}}
| colspan="2" {{na|Reserved for future use as CPU exception [[Interrupt vector table|vectors]].|align=left}}
|-
| 0x20<br>⋮<br>0xff
| 32<br>⋮<br>255
| {{na}}
| Interrupt
| {{no}}
| {{na}}
| | External interrupts.
|}