Enhanced Host Controller Interface

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EHCI (Enhanced Host Controller Interface) is the Single method of interfacing with USB 2.0. This makes life a lot easier than with USB 1.0, where 2 incompatible standards both survived. This is because the USB-IF insisted on a single implementation, produced by Intel.

Contents

Interface

On a PC you will normally find the EHCI USB controller on the PCI bus - in fact it is the only access method specified in the specification. USB 2.0 supports interfacing with USB 1.0 devices. However, EHCI is NOT expected to support them. Instead, you will find an UHCI or OHCI companion controller. Therefore you must implement OHCI and UHCI as well. Note there are NOT companions of both types, it is one type or another.

The EHCI controller will always have a PCI Class ID of 0x0C, a Subclass ID of 0x03, and an Interface value of 0x20. These values can be used to find the configuration space of the controller, which contains the memory mapped address of the EHCI registers. The address information can be found in the BAR0 PCI configuration space register.

Capability Registers

The capability registers can be found in memory at the address specified in the PCI configuration space BAR0 register.

Offset (Hex) Name Description
00 CAPLENGTH Capability Register Length
01 Reserved
02 HCIVERSION Interface Version Number (BCD)
04 HCSPARAMS Structural Parameters
08 HCCPARAMS Capability Parameters
0C HCSP-PORTROUTE Companion Port Route Description

Operation Registers

The operation registers can be found after the capability register area in memory. Add the Capability Register Length value above to the BAR0 address to find the operation register base address.

Offset (Hex) Name Description
00 USBCMD USB Command
04 USBSTS USB Status
08 USBINTR USB Interrupt Enable
0C FRINDEX USB Frame Index
10 CTRLDSSEGMENT 4G Segment Selector
14 PERIODICLISTBASE Frame List Base Address
18 ASYNCLISTADDR Next Asynchronous List Address
40 CONFIGFLAG Configured Flag Register
44 PORTSC[1-N_PORTS] Port Status/Control Register

USB Command Register

Bits Name Description
31-24 Reserved
23-16 Interrupt Threshold Number of micro frames to process between interrupts
15-12 Reserved
11 Async Schedule Park Mode Enable
10 Reserved
9-8 Async Schedule Park Mode Count
7 Light Host Controller Reset Resets the controller without affecting connected devices
6 Interrupt On Async Advance Doorbell Allows software to trigger interrupt
5 Async Schedule Enable
4 Periodic Schedule Enable
3-2 Programmable Frame List Size
1 Host Controller Reset
0 Run


USB Status Register

Bits Name Description
31-16 Reserved
15 Async Schedule Status
14 Periodic Schedule Status
13 Reclamation
12 Halted
11-6 Reserved
5 Doorbell Interrupt
4 Host System Error
3 Frame List Rollover
2 Port Change Detect
1 USB Error Interrupt
0 USB Transfer Interrupt


USB Interrupt Enable Register

Bits Name Description
31-6 Reserved
5 Async Advance Interrupt Enable
4 Host System Error Interrupt Enable
3 Frame List Rollover Interrupt Enable
2 Port Change Interrupt Enable
1 USB Error Interrupt Enable
0 USB Transfer Interrupt Enable


Port Status/Control Register

Bits Name Description
31-23 Reserved
22 Wake On Overcurrent Enable
21 Wake On Disconnect Enable
20 Wake On Connect Enable
19-16 Port Test Control
15-14 Port Indicator Control 0 = Off, 1 = Amber, 2 = Green
13 Companion Port Control 0 = Local, 1 = Companion Host Controller
12 Port Power
11-10 Line Status
9 Reserved
8 Port Reset
7 Suspend
6 Force Port Resume
5 Overcurrent Change
4 Overcurrent
3 Port Enabled Changed
2 Port Enabled
1 Connect Changed
0 Connected

Asynchronous Queue List

The asynchronous queue list is a ring of Queue Head records that point to the next Queue Head in the ring, and the first Transmit Descriptor in the queue. As long as the Asynchronous Schedule flag is set in the Command register, the EHCI controller will start with the first Queue Head located at the address in the Next Asynchronous List Address register, and process all Queue Heads until it encounters a Queue Head with the Reclaim Head flag set. The reclaim head flag is not checked on the very first Queue Head record, so you can set it's reclaim head flag, and the controller will process all Queue Heads until it reaches the first Queue Head again.

The Queue Head contains a copy of the current TD that the controller uses to process each Transfer Descriptor. This area should initially contain the first TD of the queue in the Next TD field of the TD working area.

Queue Head

Offset (Hex) Name Description
00 Horizontal Link Pointer
04 Endpoint Characteristics
08 Endpoint Capabilities
0C Current TD Address
10 Current TD Working Area This area contains as copy of the current TD data.

Horizontal Link Pointer

Bits Name Description
31-5 Next Queue Head Address of the next Queue Head in the ring
4-3 Reserved
2-1 Next Queue Type 0 = Isochronous TD, 1 = Queue Head, 2 = Split Transaction Isochronous TD, 3 = Frame Span Traversal Node
0 Terminate Set if this is the last Queue Head in a Periodic List. Not used for Asynchronous List.

Endpoint Characteristics

Bits Name Description
31-28 NAK Reload
27 Control Endpoint Not used for High Speed devices
26-16 Maximum Packet Length
15 Head of Reclamation List Set if this is the first Queue Head in an Asynchronous List
14 Data Toggle Control Set if data toggle should use value from TD
13-12 Endpoint Speed 0 = Full Speed, 1 = Low Speed, 2 = High Speed
11-8 Endpoint Number
7 Inactivate Only used in Periodic List
6-0 Device Address

Endpoint Capabilities

Bits Name Description
31-30 High Bandwidth Pipe Multiplier Must be greater than zero
29-23 Port Number Used for split transactions
22-16 Hub Address Used for split transactions
15-8 Split Completion Mask Used for split transactions
7-0 Interrupt Schedule Mask Used for split transactions



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