Interrupt Descriptor Table

The Interrupt Descriptor Table (IDT) is a binary data structure specific to the IA-32 and x86-64 architectures. It is the Protected Mode and Long Mode counterpart to the Real Mode Interrupt Vector Table (IVT) telling the CPU where the Interrupt Service Routines (ISR) are located (one per interrupt vector). It is similar to the Global Descriptor Table in structure.

The IDT entries are called gates. It can contain Interrupt Gates, Task Gates and Trap Gates.

Before you implement the IDT, make sure you have a working GDT.

IDTR

The location of the IDT is kept in the IDTR (IDT register). This is loaded using the LIDT assembly instruction, whose argument is a pointer to an IDT Descriptor structure:

IDT Descriptor (IDTR):

79 (64-bit Mode) 48 (32-bit Mode)   16	15   0
Offset 63 (64-bit Mode) 31 (32-bit Mode)   0	Size 15   0

• Size: One less than the size of the IDT in bytes.
• Offset: The linear address of the Interrupt Descriptor Table (not the physical address, paging applies).

Note that the amount of data loaded by LIDT differs in 32-bit and 64-bit modes, Offset is 4 bytes long in 32-bit mode and 8 bytes long in 64-bit mode.

This is similar to the GDT, except:

• The first entry (at zero offset) is used in the IDT.
• There are 256 interrupt vectors (0..255), so the IDT should have 256 entries, each entry corresponding to a specific interrupt vector.
• Although the IDT can contain more than 256 entries, they are ignored.
• Although the IDT can contain less than 256 entries, any entries that are not present (due to this or other reasons) will generate a General Protection Fault when an attempt to access them is made. Ideally the IDT should contain enough entries so that this fault (which is itself an interrupt vector) can be handled.

For more information, see Section 2.4.3: IDTR Interrupt Descriptor Table Register and Figure 2-6: Memory Management Registers of the Intel Software Developer Manual, Volume 3-A.

Structure on IA-32

Table

On 32-bit processors, the entries in the IDT are 8 bytes long and form a table like this:

Interrupt Descriptor Table (32-bit)

Address	Content
IDTR Offset + 0	Entry 0
IDTR Offset + 8	Entry 1
IDTR Offset + 16	Entry 2
...	...
IDTR Offset + 2040	Entry 255

The corresponding entry for a given Interrupt Vector is pointed to in memory by scaling the vector by 8 and adding it to the value in the Offset field of the IDTR.

Gate Descriptor

Each entry in the table has a complex structure:

Gate Descriptor (32-bit):

63   48	47	46   45	44	43   40	39   32
Offset 31   16	P	DPL 1   0	0	Gate Type 3   0	Reserved
31   16	15   0
Segment Selector 15   0	Offset 15   0

• Offset: A 32-bit value, split in two parts. It represents the address of the entry point of the Interrupt Service Routine.
• Selector: A Segment Selector with multiple fields which must point to a valid code segment in your GDT.
• Gate Type: A 4-bit value which defines the type of gate this Interrupt Descriptor represents. There are five valid type values:
  • 0b0101 or 0x5: Task Gate, note that in this case, the Offset value is unused and should be set to zero.
  • 0b0110 or 0x6: 16-bit Interrupt Gate
  • 0b0111 or 0x7: 16-bit Trap Gate
  • 0b1110 or 0xE: 32-bit Interrupt Gate
  • 0b1111 or 0xF: 32-bit Trap Gate
• DPL: A 2-bit value which defines the CPU Privilege Levels which are allowed to access this interrupt via the INT instruction. Hardware interrupts ignore this mechanism.
• P: Present bit. Must be set (1) for the descriptor to be valid.

For more information, see Section 6.11: IDT Descriptors and Figure 6-2: IDT Gate Descriptors of the Intel Software Developer Manual, Volume 3-A.

Example Code

C Struct:

struct InterruptDescriptor32 {
   uint16_t offset_1;        // offset bits 0..15
   uint16_t selector;        // a code segment selector in GDT or LDT
   uint8_t  zero;            // unused, set to 0
   uint8_t  type_attributes; // gate type, dpl, and p fields
   uint16_t offset_2;        // offset bits 16..31
};

Example type_attributes values that people are likely to use (assuming DPL is 0):

• 32-bit Interrupt Gate: 0x8E (p=1, dpl=0b00, type=0b1110 => type_attributes=0b1000_1110=0x8E)
• 32-bit Trap Gate: 0x8F (p=1, dpl=0b00, type=0b1111 => type_attributes=1000_1111b=0x8F)
• Task Gate: 0x85 (p=1, dpl=0b00, type=0b0101 => type_attributes=0b1000_0101=0x85)

Structure on x86-64

Table

On 64-bit processors, the entries in the IDT are 16 bytes long and form a table like this:

Interrupt Descriptor Table (64-bit)

Address	Content
IDTR Offset + 0	Entry 0
IDTR Offset + 16	Entry 1
IDTR Offset + 32	Entry 2
...	...
IDTR Offset + 4080	Entry 255

The corresponding entry for a given Interrupt Vector is pointed to in memory by scaling the vector by 16 and adding it to the value in the Offset field of the IDTR.

Gate Descriptor

Each entry in the table has a complex structure:

Gate Descriptor (64-bit):

127   96
Reserved
95   64
Offset 63   32
63   48	47	46   45	44	43   40	39   35	34   32
Offset 31   16	P	DPL 1   0	0	Gate Type 3   0	Reserved	IST 2   0
31   16	15   0
Segment Selector 15   0	Offset 15   0

• Offset: A 64-bit value, split in three parts. It represents the address of the entry point of the Interrupt Service Routine.
• Selector: A Segment Selector with multiple fields which must point to a valid code segment in your GDT.
• IST: A 3-bit value which is an offset into the Interrupt Stack Table, which is stored in the Task State Segment. If the bits are all set to zero, the Interrupt Stack Table is not used.
• Gate Type: A 4-bit value which defines the type of gate this Interrupt Descriptor represents. In long mode there are two valid type values:
  • 0b1110 or 0xE: 64-bit Interrupt Gate
  • 0b1111 or 0xF: 64-bit Trap Gate
• DPL: A 2-bit value which defines the CPU Privilege Levels which are allowed to access this interrupt via the INT instruction. Hardware interrupts ignore this mechanism.
• P: Present bit. Must be set (1) for the descriptor to be valid.

In your Interrupt Service Routines, remember to return from the interrupt using the IRETQ instruction instead of IRET, as assemblers will not translate that for you. Many 64-bit IDT related problems on the forum are caused by that missing 'Q'. Don't let this happen to you.

For more information, see Section 6.14.1: 64-Bit Mode IDT and Figure 6-8: 64-Bit IDT Gate Descriptors of the Intel Software Developer Manual, Volume 3-A.

Example Code

C Struct:

struct InterruptDescriptor64 {
   uint16_t offset_1;        // offset bits 0..15
   uint16_t selector;        // a code segment selector in GDT or LDT
   uint8_t  ist;             // bits 0..2 holds Interrupt Stack Table offset, rest of bits zero.
   uint8_t  type_attributes; // gate type, dpl, and p fields
   uint16_t offset_2;        // offset bits 16..31
   uint32_t offset_3;        // offset bits 32..63
   uint32_t zero;            // reserved
};

Example type_attributes values that people are likely to use (assuming DPL is 0):

• 64-bit Interrupt Gate: 0x8E (p=1, dpl=0b00, type=0b1110 => type_attributes=0b1000_1110=0x8E)
• 64-bit Trap Gate: 0x8F (p=1, dpl=0b00, type=0b1111 => type_attributes=1000_1111b=0x8F)

IDT items

Originally created for Wikipedia. [1]

Copied from: [2]

This table contains information collected from the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3 (3A, 3B, 3C & 3D): System Programming Guide revision from April 2022.

x86 Interrupt descriptor table items [edit table]

Int. №		Mnem.	Type	Err. code	Name	Source
hex	dec
0x00	0	#DE	Fault	No	Divide Error	DIV and IDIV instructions.
0x01	1	#DB	Trap	No	Debug Exception	Instruction, data, and I/O breakpoints; single-step; and others.
0x02	2	NMI	Interrupt	No	NMI Interrupt	Nonmaskable external interrupt.
0x03	3	#BP	Trap	No	Breakpoint	INT3 instruction.
0x04	4	#OF	Trap	No	Overflow	INTO instruction.
0x05	5	#BR	Fault	No	BOUND Range Exceeded	BOUND instruction.
0x06	6	#UD	Fault	No	Invalid Opcode (Undefined Opcode)	UD instruction or reserved opcode.
0x07	7	#NM	Fault	No	Device Not Available (No Math Coprocessor)	Floating-point or WAIT/FWAIT instruction.
0x08	8	#DF	Abort	Yes (zero)	Double Fault	Any instruction that can generate an exception, an NMI, or an INTR.
0x09	9	N/A	Fault	No	Coprocessor Segment Overrun (reserved)	Floating-point instruction.
0x0A	10	#TS	Fault	Yes	Invalid TSS	Task switch or TSS access.
0x0B	11	#NP	Fault	Yes	Segment Not Present	Loading segment registers or accessing system segments.
0x0C	12	#SS	Fault	Yes	Stack-Segment Fault	Stack operations and SS register loads.
0x0D	13	#GP	Fault	Yes	General Protection	Any memory reference and other protection checks.
0x0E	14	#PF	Fault	Yes	Page Fault	Any memory reference.
0x0F	15	N/A		No	Intel reserved. Do not use.
0x10	16	#MF	Fault	No	x87 FPU Floating-Point Error (Math Fault)	x87 FPU floating-point or WAIT/FWAIT instruction.
0x11	17	#AC	Fault	Yes (zero)	Alignment Check	Any data reference in memory.
0x12	18	#MC	Abort	No	Machine Check	Error codes (if any) and source are model dependent.
0x13	19	#XM	Fault	No	SIMD Floating-Point Exception	SSE/SSE2/SSE3 floating-point instructions
0x14	20	#VE	Fault	No	Virtualization Exception	EPT violations
0x15	21	#CP	Fault	Yes	Control Protection Exception	RET, IRET, RSTORSSP, and SETSSBSY instructions can generate this exception. When CET indirect branch tracking is enabled, this exception can be generated due to a missing ENDBRANCH instruction at target of an indirect call or jump.
0x16 ⋮ 0x1f	22 ⋮ 31	N/A			Reserved for future use as CPU exception vectors.
0x20 ⋮ 0xff	32 ⋮ 255	N/A	Interrupt	No	N/A	External interrupts.

Gate Types

There are basically two kinds of interrupts: ones that occur when code execution has encountered an Exception due to bad code, or ones that occur to handle events unrelated to currently executing code. In the first case it is pertinent to save the address of the currently executing instruction so that it can be retried, these are called Traps. In the second case it is pertinent to save the address of the next instruction so that execution can be resumed where it left off. These could be caused by an IRQ or other hardware event, or by use of the INT instruction. Another difference to note is that with Traps, new interrupts might occur during the service routine, but when the CPU is serving an IRQ, further interrupts are masked until an End of Interrupt signal is sent. How a certain interrupt is served depends on which kind of gate you put in the IDT entry.

Interrupt Gate

An Interrupt Gate is used to specify an Interrupt Service Routine. For example, when the assembly instruction INT 50 is performed while running in protected mode, the CPU looks up the 50th entry (located at 50 * 8) in the IDT. Then the Interrupt Gate's Selector and Offset values are loaded. The Selector and Offset are used to call the Interrupt Service Routine. When the IRET instruction is performed, the CPU returns from the interrupt. If the CPU was running in 32-bit mode and the specified selector is a 16-bit gate, then the CPU will go in 16-bit Protected Mode after calling the ISR. To return in this case, the O32 IRET instruction should be used, or else the CPU will not know that it should do a 32-bit return (reading 32-bit values off the stack instead of 16 bit).

Trap Gate

A Trap Gate should be used to handle Exceptions. When such an exception occurs, there can sometimes be an error code placed on the stack, which should be popped before returning from the interrupt.

Trap Gates and Interrupt Gates are similar, and their descriptors are structurally the same, differing only in the Gate Type field. The difference is that for Interrupt Gates, interrupts are automatically disabled upon entry and reenabled upon IRET, whereas this does not occur for Trap Gates.

Task Gate

A Task Gate is a gate type specific to IA-32 that is used for hardware task switching. For a Task Gate the Selector value should refer to a position in the GDT which specifies a Task State Segment rather than a code segment, and the Offset value is unused and should be set to zero. Rather than jumping to a service routine, when the CPU processes this interrupt, it will perform a hardware task switch to the specified task. A pointer back to the task which was interrupted will be stored in the Task Link field in the TSS.

"*NOTE* Because IA-32 tasks are not re-entrant, an interrupt-handler task must disable interrupts between the time it completes handling the interrupt and the time it executes the IRET instruction. This action prevents another interrupt from occurring while the interrupt task's TSS is still marked busy, which would cause a general-protection (#GP) exception." —Intel Software Developer Manual

This type of gate is not often used as hardware task switching is slow and has little to no optimization on modern processors. As well, it has been entirely removed on x86-64.

See Also

Articles

• GDT
• IDT problems

External References

• Michal Ludvig's Intel 80386 Programmer's Reference Manual chapter 9