CPU Registers x86

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Contents

General Purpose Registers

32 bit 16 bit 8 high bit 8 low bit description
eax ax ah al accumulator
ebx bx bh bl base
ecx cx ch cl counter
edx dx dh dl data
esi si N/A N/A source index
edi di N/A N/A destination index
ebp bp N/A N/A base pointer
esp sp N/A N/A stack pointer

Pointer Registers

32 bit 16 bit description
eip ip instruction pointer

Segment Registers

16 bit description
cs code segment
ds data segment
es extra segment
ss stack segment
fs general purpose f segment
gs general purpose g segment

EFLAGS Register

bit label description
0 cf carry flag
2 pf parity flag
4 af auxiliary flag
6 zf zero flag
7 sf sign flag
8 tf trap flag
9 if interrupt flag
10 df direction flag
11 of overflow flag
12-13 iopl i/o privilege level
14 nt nested task flag
16 rf resume flag
17 vm virtual 8086 mode flag
18 ac alignment check flag
19 vif virtual interrupt flag
20 vip virtual interrupt pending
21 id id flag

Control Registers

CR0

bit label description
0 pe protected mode enable
1 mp monitor co-processor
2 em emulation
3 ts task switched
4 et extension type
5 ne numeric error
16 wp write protect
18 am alignment mask
29 nw not-write through
30 cd cache disable
31 pg paging

NOTE that this register is the only control register that can be written and read via 2 ways unlike the other that can be accessed only via the MOV instruction

;way 1:
;write:
mov cr0,reg
;read:
mov reg,cr0 
;----------------------
;way 2:
;write:
lmsw reg
 
;read:
smsw reg

CR1

Reserved, the cpu will throw a #ud exeption when trying to access them.

CR2

bit label description
0-31 pfla page fault linear address

CR3

bit description PAE mode long mode
0-31 physical base address of page directory base of PDPT base of PML4T

Note that this must be page aligned

CR4

bit label description
0 vme virtual 8086 mode extensions
1 pvi protected mode virtual interrupts
2 tsd time stamp disable
3 de debugging extensions
4 pse page size extension
5 pae physical address extension
6 mce machine check exception
7 pge page global enable
8 pce performance monitoring counter enable
9 osfxsr os support for fxsave and fxrstor instructions
10 osxmmexcpt os support for unmasked simd floating point exceptions
11 umip user mode instruction prevention (#GP on SGDT, SIDT, SLDT, SMSW, and STR instructions when CPL > 0)
13 vmxe virtual machine extensions enable
14 smxe safer mode extensions enable
17 pcide pcid enable
18 osxsave xsave and processor extended states enable
20 smep supervisor mode executions protection enable
21 smap supervisor mode access protection enable

CR5 - CR7

Reserved, same case as CR1.

Debug Registers

DR0 - DR3

Contain linear addresses of up to 4 breakpoints. If paging is enabled, they are translated to physical addresses.

DR6

It permits the debugger to determine which debug conditions have occurred.
Bits 0 through 3 indicates, when set, that it's associated breakpoint condition was met when a debug exception was generated.
Bit 13 indicates that the next instruction in the instruction stream accesses one of the debug registers.
Bit 14 indicates (when set) that the debug exception was triggered by the single-step execution mode (enabled with TF bit in EFLAGS).
Bit 15 indicates (when set) that the debug instruction resulted from a task switch where T flag in the TSS of target task was set.
Bit 16 indicates (when clear) that the debug exception or breakpoint exception occured inside an RTM region.

DR7

bit description
0 local DR0 breakpoint
1 global DR0 breakpoint
2 local DR1 breakpoint
3 global DR1 breakpoint
4 local DR2 breakpoint
5 global DR2 breakpoint
6 local DR3 breakpoint
7 global DR3 breakpoint
16-17 conditions for DR0
18-19 size of DR0 breakpoint
20-21 conditions for DR1
22-23 size of DR1 breakpoint
24-25 conditions for DR2
26-27 size of DR2 breakpoint
28-29 conditions for DR3
30-31 size of DR3 breakpoint

A local breakpoint bit deactivates on hardware task switches, while a global does not.
00b condition means execution break, 01b means a write watchpoint, and 11b means an R/W watchpoint. 10b is reserved for I/O R/W (unsupported).

Test Registers

name description
TR3 - TR5 undocumented
TR6 test command register
TR7 test data register

Protected Mode Registers

GDTR

bits label description
0-15 limit (size of GDT) - 1
16-47 base starting address of GDT

Stores the segment selector of the GDT.

LDTR

bits label description
0-15 limit (size of LDT) - 1
16-47 base starting address of LDT

Stores the segment selector of the LDT.

IDTR

bits label description
0-15 limit (size of IDT) - 1
16-47 base starting address of IDT

Stores the segment selector of the IDT.

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