IBM Mainframe architecture
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The IBM Mainframe architecture (spanning System/360, System/370, 370-XA, ESA/370, System/390, and modern z/Architecture / s390x) represents the longest continuously evolving computing architecture in history (1964–present).
Unlike workstation or commodity microcomputer architectures (x86, ARM, RISC-V) which focus primarily on general-purpose compute pipelines, the mainframe architecture is fundamentally system-driven. It was engineered from the ground up around massive I/O throughput, high-reliability enterprise business workloads, dynamic hardware virtualization, coprocessor offloading, and strict binary backward compatibility across six decades.
The "31-Bit Architecture" Misconception
A widespread misconception among software developers is that legacy mainframes were "31-bit architectures" with 31-bit registers.
From System/360 (1964) to ESA/390 (1990), the architecture has always had 32-bit General Purpose Registers (GPRs 0–15) and 32-bit ALU operations.
What changed over the decades was not the register width, but the Storage Addressing Mode (AMODE) and physical address bus width:
| Architecture Generation | Year | GPR Width | Virtual Addressing | Physical / Real Addressing | Addressing Mode (AMODE) |
|---|---|---|---|---|---|
| System/360 | 1964 | 32-bit | 24-bit (Model 67: 24/32-bit) | 24-bit (16 MiB max) | AMODE 24 |
| System/370 | 1970 | 32-bit | 24-bit (16 MiB) | 24-bit (Some models: 26-bit / 64 MiB) | AMODE 24 |
| System/370-XA | 1983 | 32-bit | 24-bit / 31-bit (2 GiB) | 31-bit (2 GiB) | Bimodal: AMODE 24, AMODE 31 |
| ESA/370 & ESA/390 | 1988 / 1990 | 32-bit | 31-bit + Access Registers (16 x 2 GiB) | 31-bit (Later models: 36-bit) | AMODE 24, AMODE 31, AR Mode |
| z/Architecture (s390x) | 2000–Present | 64-bit | 24-bit / 31-bit / 64-bit (16 EiB) | 64-bit | Trimodal: AMODE 24, AMODE 31, AMODE 64 |
Why 31-Bit Addressing?
When IBM introduced 370-XA in 1983 to break past the 16 MiB barrier of 24-bit addressing, programs frequently abused the unused top 8 bits of 32-bit address words in memory to store application flags and status tags.
To preserve compatibility while allowing 2 GiB address spaces, IBM adopted a 31-bit address scheme. Bit 0 (the MSB in IBM notation) of a 32-bit address was reserved as an Addressing Mode (AMODE) indicator:
- If bit 0 was `0`, the CPU operated in 24-bit mode (wrapping at 16 MiB).
- If bit 0 was `1`, the CPU operated in 31-bit mode (allowing access up to 2 GiB).
Chronological Architecture Evolution
1. System/360 (1964): The Foundation
Introduced by Gene Amdahl, Fred Brooks, and Gerrit Blaauw, the S/360 unified scientific and commercial computing into a single scalable architecture:
- Standardized the 8-bit byte, byte-addressable memory, and 2's complement 32-bit integers.
- Introduced 16 General Purpose Registers (GPR0–GPR15), 4 Floating-Point Registers (FPRs), and the Program Status Word (PSW).
- Introduced asynchronous I/O Channels (Selector, Byte Multiplexer).
- System/360 Model 67 (1967): Added the first dynamic address translation (DAT) hardware for paging and virtual memory under TSS/360 and CP-67 (the ancestor of modern VM hypervisors).
2. System/370 (1970): Virtual Storage Standardization
- Standardized DAT across the entire enterprise product line.
- Introduced dual-space virtual memory and inter-CPU signaling for multiprocessing.
- Introduced the Extended Control (EC) Mode PSW.
- Extended physical memory bus addressing from 24 bits to 26 bits (Extended Real Addressing / ERA, 64 MiB) on high-end models (3033, 3081).
3. System/370 Extended Architecture / 370-XA (1983)
- Introduced 31-bit virtual and real storage addressing, breaking the 16 MiB memory limit and expanding addressability to 2 GiB.
- Introduced the Channel Subsystem (CSS): dedicated channel processors independent of specific CPU attachments.
- Bimodal program execution (seamlessly switching between AMODE 24 and AMODE 31 via `BSM` and `BASSM`).
4. ESA/370 (1988) & ESA/390 (1990)
- Introduced Enterprise Systems Architecture.
- Access Registers (AR Mode): Added 16 Access Registers (AR0–AR15). When in AR mode, instructions can access data across up to 16 separate 2 GiB virtual address spaces (Data Spaces) simultaneously without swapping CR1 page tables.
- PR/SM (Processor Resource/Systems Manager): Bare-metal hardware partitioning (LPARs) built directly into the machine firmware.
- CMOS Transition (1994): Transitioned mainframe hardware from hot, water-cooled Bipolar/ECL chips to air-cooled CMOS microprocessors (IBM 9672 generation).
5. z/Architecture (2000–Present)
- Expanded GPRs, FPRs, Control Registers, and addressing from 32 bits to full 64 bits.
- Trimodal execution (24-bit, 31-bit, and 64-bit applications running concurrently on the same OS kernel).
- Replaced the 8-byte PSW with the 16-byte Extended PSW (`LPSWE`).
- Continual modern extensions: SIMD/Vector facilities, transactional memory (TX), hardware cryptographic acceleration (CPACF), on-chip AI neural processing units (Telum / z16).
Taxonomy: Architecture vs. Hardware Brands vs. OS Triples
Because the mainframe ecosystem separates the ISA specification from marketing product lines and software toolchains, the naming conventions can be confusing:
| Layer | Name | Description / Examples |
|---|---|---|
| ISA Specification | System/360, System/370, 370-XA, ESA/370, ESA/390, z/Architecture |
The formal architectural standard (defined in the Principles of Operation manuals). |
| Hardware Brands (Historical) | S/360, S/370, 303x, 308x, 3090, ES/9000, System/390 (S/390), IBM 9672, Multiprise |
Marketing and physical server family names. |
| Hardware Brands (Modern) | eServer zSeries (z900/z990), System z (z9/z10), zEnterprise (z196/zEC12), IBM z13, z14, z15, z16 |
Physical servers implementing modern 64-bit z/Architecture. |
| GCC / Linux Target (31-bit) | s390-ibm-linux-gnu (or simply s390) |
Linux running in legacy 31-bit ESA/390 compatibility mode. |
| GCC / Linux Target (64-bit) | s390x-ibm-linux-gnu (or simply s390x) |
Standard modern 64-bit Linux on z/Architecture. |
The "System-Driven" Philosophy: Multi-Engine Co-Processors
Commodity PC architectures typically utilize symmetric multiprocessors where every CPU core runs operating system kernel code. In contrast, an IBM Mainframe processor drawer is an asymmetric, multi-engine computing complex.
All physical cores on a modern mainframe processor chip (e.g. z15, z16) share identical silicon, but are designated at initialization (or dynamically reassigned) to specialized operational roles:
1. CP (Central Processor)
The standard general-purpose engine. Runs standard operating systems (z/OS, Linux, z/VSE, z/TPF) and executes all standard user/kernel workloads.
2. SAP (System Assist Processor)
Dedicated I/O offload processors.
- The operating system does not service raw hardware device interrupts or manage physical bus transfers directly.
- When an OS issues an I/O request (`SSCH` - Start Subchannel), the CPU immediately offloads the entire Channel Program (a list of CCWs) to the **SAP**.
- The SAP independently manages the data movement through the **Channel Subsystem (CSS)**, verifies checksums, arbitrates fiber/PCIe links, and only interrupts the OS CP when the transaction is completed.
3. IFL (Integrated Facility for Linux)
Dedicated cores reserved exclusively for running Linux and KVM on IBM zSystems. IFLs are physically identical to CPs, but are restricted from running proprietary IBM z/OS workloads, allowing them to be sold and licensed at substantially lower software-maintenance price tiers.
4. zIIP (Integrated Information Processor)
Specialized coprocessors designed to run compute-intensive enterprise background workloads (such as Java JVM execution, XML parsing, DB2 indexing, and IPSec encryption) to prevent general CPs from being bogged down.
5. ICF (Internal Coupling Facility)
Dedicated hardware engines used for Parallel Sysplex clustering. They run specialized coupling-control code to synchronize memory caches, distributed locks, and buffer pools across multiple physically separate mainframe servers at microsecond latency.
6. Hardware Accelerators
- CPACF (Central Processor Assist for Cryptographic Functions): On-core hardware crypto accelerators (AES, SHA-1/2/3, DES) executed via dedicated unprivileged machine instructions (e.g., `KM`, `KMC`, `KLMD`).
- CEX (Crypto Express): Tamper-proof HSM PCIe adapters handling high-security RSA, ECC, and quantum-safe key generation.
- On-Chip AI Accelerator: Built-in neural network processing pipelines integrated on each core chip (introduced in Telum / z16) providing real-time AI inference during transaction processing.
Core Architectural Concepts
PR/SM and Hardware Virtualization
There is effectively no "bare-metal OS execution" in modern mainframe computing. Every system runs on top of PR/SM (Processor Resource/Systems Manager), a Type-0 hypervisor implemented in firmware/millicode. PR/SM manages LPARs (Logical Partitions) with guaranteed hardware isolation, dynamic resource allocation, and zero hypervisor latency.
Storage Keys and Complex Memory Protection
In addition to page-table (DAT) permissions, z/Architecture features a separate, hardware-enforced memory security layer known as Storage Keys:
- Every 4 KiB physical memory frame has an associated 7-bit hardware storage key in the memory controller:
- Bits 0–3: Access-Control Key (0–15)
- Bit 4: Fetch-Protection Bit (1 = read access also requires key match)
- Bit 5: Reference Bit (Set whenever the page is accessed)
- Bit 6: Change Bit (Set whenever the page is written)
- If the PSW Key does not match the page's storage key (and the PSW Key is not 0), any memory load or store instantly triggers a hardware protection exception (`PGM_PROTECTION`), independent of virtual memory page tables.
Channel Subsystem (CSS) and CCWs
Mainframes do not use memory-mapped I/O (MMIO) or register-based polling. Instead, all I/O is managed via Channel Command Words (CCWs):
- The OS builds a linked list of I/O commands (CCWs) in memory.
- The OS issues
SSCH(Start Subchannel) passing the subchannel ID and ORB (Operation Request Block). - The SAP processor processes the entire chain independently.
- Upon completion, an I/O interruption is posted to the OS containing the Final Status (IRB).
Sixty Years of Backward Compatibility
A fundamental hallmark of the mainframe architecture is complete, unbroken binary compatibility:
- A non-privileged application binary compiled for an original IBM System/360 in 1964 can run without recompilation or emulation on a modern IBM z16 (2022) running in 24-bit compatibility mode.
- The instruction set architecture has preserved opcodes, condition codes, arithmetic behaviors, and lowcore conventions while scaling from 16 KiB magnetic core memory to multi-terabyte NUMA complexes.