Itanium2 Overview

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The Itanium and Itanium2 utilize the E.P.I.C. (Explicitly Parallel Instruction Computing) architecture. The instruction pipeline in the Itanium2 is 8 stages deep. The first 2 (IPG and ROT) are the "front end" and the remaining 6 (EXP, REN, REG, EXE, DET, and WRB) make up the "back end" of the instruction pipeline.

Instructions are packed into 128-bit bundles. Each bundle has a 5-bit template specifier that notifies the CPU of what each of the encapsulated instructions are. Each instruction is 41-bits wide and can be paired up in some bundle types (called LX Units) to form an 82-bit instruction (to allow for full 64-bit immediate values). There are 12 non-reserved bundle template formats specified by Intel.

There are 5 different instruction types: ALU (Arithmetic Logic Unit), M (Memory), I (non-ALU Integer), F (Floating-point) and B (Branch). There is another logical type that is actually just an extension of one of those other 5 types called LX (Extended).

The Itanium2 can execute up to 6 instructions per clock cycle (2 full instruction bundles) in parallel. Sometimes issuing 6 instructions in parallel is just not possible, these are called "split issues". Split issues occur when an explicit "stop" is set by software (it lets the CPU know that the upcoming instruction needs to be issued next cycle) or by the CPU running out of usable resources for an instruction to use.


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