The Motorola 68000 family of processors were very popular in home computers from the late 1980s to the early 1990s. It was used in such well-known systems as the Amiga, Atari ST, and Macintosh, and was also the processor of choice in the majority of workstation-class Unix systems of the time. The architecture has also found a myriad of other, more recent, uses, such as the 68000 in the Sega Genesis, being present in a radiation-hardened form in the US space shuttle, and, in the form of the simplified DragonBall embedded processor, for Palm devices up until OS 4.
The 68k architecture was/is long lived, and has gone through many iterations. Most programmer-visible characteristics, however, stayed the same throughout the architecture's history. It is an internally 32 bit CISC design, from the 68000 used in the first Macintosh up until the 68060 used in the latest 68k Amiga accelerators made. Every 68k processor has exactly two privilege modes: supervisor and user.
There are 8 registers each of address and data registers, A0-A7 and D0-D7, the status register SR (analogous to the x86 FLAGS register), and the program counter PC (analogous to the x86 EIP register). All registers excepting SR, which is 16 bits, are 32-bit. All data registers are general purpose registers. The address registers are generally used as pointers, but can be used to store extra data with no ill effects. As defined by the architecture, only one address register, A7, has a predefined purpose. A7 is the stack register, and the stack opcodes (PEA, LINK, UNLK) do modify this register implicitly.
The 68k instruction set is mostly orthogonal, with most instructions allowing all addressing modes with all operand sizes. The architecture allows for direct, immediate, address register indirect, and PC-relative addressing modes. The best description of the operation of these is in the 68k family programmers' reference manual, linked at the bottom of the article.
Aside from the near-orthogonality, the 68k processor family presents a typical CISC instruction set. It uses dyadic instructions, as per x86, where, for most instructions, there is a source operand and a destination operand, where the operation is performed between the two and the result is stored in the destination.
move.l #2, d0 addi.l #3, d0
This fragment would result in 5 being stored in register d0.
The original 68k processor. This processor had only 24-bit external addressing, allowing up to 16MB of memory to be directly addressable. It lacked an MMU or the ability to interface with one, so was incapable of memory protection or mapping, aside from some Unix workstations that hacked a solution up using two 68000s executing the same code in parallel. It was available as the 68000, with a 16-bit data bus (as used in the Lisa, Macintosh, Atari ST, and Amiga), or as the 68008, with an 8-bit data bus, meant to drop into 6800-based logic boards to reduce engineering costs (as used in the Sinclair QL).
This was a minor iteration that made MOVE from SR a privileged instruction, added the ability to recover from bus faults, making MMU interfacing a possibility, and made the interrupt vectors movable.
This iteration added a 32-bit ALU and added the option of 32-bit address and data buses (lacking in the EC model). It also added some NUMA multiprocessing support. It was marketed alongside the optional 68851 MMU and 68881/68882 FPUs.
This iteration simply added 256-byte instruction and data caches, and brought the 68851 MMU on-chip (lacking in the EC model). It was still marketed alongside the optional 68881/68882 FPUs.
The 68040 was a major upgrade. It brought both the FPU (lacking in the LC model) and MMU on-chip (both lacking in the EC model), added instruction pipelining, and larger (4k each), faster caches.
This processor was very similar to the '040. It added larger caches and dual pipelining.
These were embedded SoCs based on a 68000 core. They had color/greyscale LCD, PC speaker-style device, UART, UART bootstrap, RTC, and touchscreen controllers built in along with flash and RAM.
These are a departure from the rest of the line. They are based on a 68000 core, but have been simplified. Floating point intermediates are reduced from 80-bit to 64-bit, some uncommonly-used instructions and addressing modes are removed, and instruction word length has been regulated to only 16, 32, or 48-bit lengths.