RISC-V Bare Bones
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RISC-V is a instruction set architecture, fully opensource. The ISA has a bunch of extensions, in this tutorial we will assume that imad are available.
At our disposal we will have a generic board we will program for: virt. This board is available for QEMU.
You can obtain a riscv64 gcc toolchain on kernel.org; Designing an operating system for this architecture is not complicated and is pretty straight forward:
kernel.c
The thing we will make here is a simple serial port output/reader.
#include <stdint.h>
#include <stddef.h>
unsigned char * uart = (unsigned char *)0x10000000;
void putchar(char c) {
*uart = c;
return;
}
void print(const char * str) {
while(*str != '\0') {
putchar(*str);
str++;
}
return;
}
void kmain(void) {
print("Hello world!\r\n");
while(1) {
// Read input from the UART
putchar(*uart);
}
return;
}
This will print a simple "Hello world!" and a newline following, after that it will echo any input given to the serial port.
entry.S
Be wary we are just setting up stack and jumping into kernel. It's the kernel's job to set up IRQs and other system stuff
.section .init
.option norvc
.type start, @function
.global start
start:
.cfi_startproc
.option push
.option norelax
la gp, global_pointer
.option pop
/* Reset satp */
csrw satp, zero
/* Setup stack */
la sp, stack_top
/* Clear the BSS section */
la t5, bss_start
la t6, bss_end
bss_clear:
sd zero, (t5)
addi t5, t5, 8
bltu t5, t6, bss_clear
la t0, kmain
csrw mepc, t0
/* Jump to kernel! */
tail kmain
.cfi_endproc
.end
Take in account that you need to implement a type of locking if you want to support SMP, and implement a trampoline or a jail for the CPUs. Be wary that we haven't enabled interrupts just yet and any return from kmain will result in invalid opcodes being executed.
linker.ld
We need to specify where our kernel will be loaded at. For this example we will use the start of the RAM as our load address.
ENTRY(start);
. = 0x80000000;
SECTIONS {
/* Include entry point at start of binary */
.text : ALIGN(4K) {
*(.init);
*(.text);
}
.bss : ALIGN(4K) {
PROVIDE(bss_start = .);
*(.bss);
. += 4096;
PROVIDE(stack_top = .);
. += 4096;
PROVIDE(global_pointer = .);
PROVIDE(bss_end = .);
}
.rodata : ALIGN(4K) {
*(.rodata);
}
.data : ALIGN(4K) {
*(.data);
}
}
Final
The process is pretty straightforward:
riscv64-elf-gcc -Wall -Wextra -c -mcmodel=medany kernel.c -o kernel.o -ffreestanding
riscv64-elf-as -c entry.S -o entry.o
riscv64-elf-ld -T linker.ld -lgcc -nostdlib kernel.o entry.o -o kernel.elf
Once this is done, the kernel can be run with the following:
qemu-system-riscv64 -machine virt -bios none -kernel kernel.elf -serial mon:stdio
You will promptly see a terminal with the "Hello world!" and you can "write stuff" to it. A serial terminal is very "boring", but you still have a lot at your disposal, you have a PLIC, a CLIC and a bunch of opportunities to learn PCI internals.
Going further
- Store input somewhere for later processing (i.e: "echo" command)
- Implement SMP support, for now our basic kernel will crash on any multicore system
- QEMU will give FDT in register a1. Use libfdt to parse the tree to avoid nightrames
- Implement a heap
- Enable Sv39 paging
- SMP support
- Manage IRQs
- You have a PIO and a MMIO window at your disposal, use them wisely, you will also have to face the PCIe ECAM, for your sanity: Do not implement bridges
See also
- PCI Express
- HiFive-1 Bare Bones
- RISC-V Meaty Skeleton with QEMU virt board
- RISC-V instruction set
- Small Bare Metal RISCV OS in asm and Rust
- Page of above with asm code setting up different kernel stack for each hart
- Selfie: a minimalist self hosting compiler, riscv64 os, and simulator
- Selfie page includes 2 well written bare-metal theses
- Complete open source Microkernel for riscv64 (also arm7, ia32) plus support code
- XV6: a reimplementation of original Unix for teaching riscv64 OS development
- Port of XV6 to execute on VisionFive 2 SoC
- Wonderfully clear and detailed base level port how2: NuttX RTOS to Star64 SoC