User contributions for Demindiro

23 June 2026

• 19:3419:34, 23 June 2026 diff hist +28‎ Rump kernel ‎ Add Template:Kernel designs current
• 19:3319:33, 23 June 2026 diff hist +748‎ N Rump kernel ‎ Just collecting links, haven't looked at them too closely
• 19:2619:26, 23 June 2026 diff hist +22‎ Template:Kernel designs ‎ Add rump kernel current

21 June 2026

• 12:2112:21, 21 June 2026 diff hist +849‎ N RISC-V IOMMU ‎ Cursory research in how RISC-V IOMMU (and AIA) handles MSIs current

20 June 2026

• 22:2622:26, 20 June 2026 diff hist +191‎ AMD-Vi IOMMU ‎ Cursory research in special MSI / MSI-X address ranges for this IOMMU current
• 22:2222:22, 20 June 2026 diff hist +25‎ AMD-Vi IOMMU ‎ →‎External Links: Fix broken link + new version of specification
• 21:3921:39, 20 June 2026 diff hist +2‎ m Intel VT-d ‎ →‎Emulation: info mtree should be under QEMU section current
• 21:3921:39, 20 June 2026 diff hist +782‎ Intel VT-d ‎ Write requests to 0xFEEx_xxxx are special and not translated by DMA tables :(

19 June 2026

• 21:4621:46, 19 June 2026 diff hist +6‎ Intel VT-d ‎ →‎QEMU: short-form options are deprecated

18 June 2026

• 21:5621:56, 18 June 2026 diff hist +5‎ Intel VT-d ‎ →‎Scalable Mode PASID structures
• 21:5421:54, 18 June 2026 diff hist +7‎ Intel VT-d ‎ →‎Scalable Mode PASID structures: Worth noting that PASID is PCIe terminology (from what I find around the internet. I'd link to the spec if I had one...)
• 21:5221:52, 18 June 2026 diff hist +1‎ m Intel VT-d ‎ →‎= (Lower/Upper) Context Table
• 21:5121:51, 18 June 2026 diff hist +1,076‎ Intel VT-d ‎ →‎Translation structures: brief description of relevant structures
• 21:3921:39, 18 June 2026 diff hist +340‎ Intel VT-d ‎ QEMU device settings

17 June 2026

• 21:5521:55, 17 June 2026 diff hist +569‎ Intel VT-d ‎ Note about compatibility with x86 page tables

15 June 2026

• 19:1719:17, 15 June 2026 diff hist +487‎ N Intel VT-d ‎ Created page with "{{stub}} Intel VT-d provides an IOMMU to translate device addresses to host addresses, similar to the MMU on the CPU. It is also able to remap interrupt lines. The location of the configuration registers can be found in the DMAR ACPI table. == See also == === External Links === * [https://cdrdv2-public.intel.com/671081/vt-directed-io-spec.pdf Intel® Virtualization Technology for Directed I/O (June 2022 Revision 4.0)] Category:X86 Virtualization Categ..."

9 March 2026

• 19:1319:13, 9 March 2026 diff hist +1,916‎ N User:Demindiro/Encryption ‎ Created page with "As computers are increasingly interconnected and attacks become more sophisticated it is necessary to secure data both at rest and in transit. Much of this is done in software on the CPU, but this does not cover all hardware (such as DRAM) and may add substantial overhead. Modern hardware often includes This page documents support for encryption at various layers of common hardware and how to take advantage of it in the design of an OS. == Storage devices (HDD / SSD)..." current

24 February 2026

• 19:5019:50, 24 February 2026 diff hist +315‎ AMD-Vi IOMMU ‎ note that DMA remap needs to be explicitly enabled in QEMU
• 18:1418:14, 24 February 2026 diff hist +3,019‎ N Talk:AMD-Vi IOMMU ‎ Created page with "== QEMU AMD-Vi IOMMU confusion == There are several aspects about the IOMMU that I'm uncertain about, so I won't put them in the article while I query qemu-devel. In the meantime, I will document them here: === INVALIDATE_IOMMU_ALL doesn't reload DTEs === The specification says (emphasis mine): <blockquote> The INVALIDATE_IOMMU_ALL command instructs the IOMMU to invalidate all cached information for interrupt remapping and address translation for guest and nested tra..." current

20 February 2026

• 21:3321:33, 20 February 2026 diff hist +1,474‎ AMD-Vi IOMMU ‎ →‎Device table: These names...
• 21:1721:17, 20 February 2026 diff hist +681‎ AMD-Vi IOMMU ‎ Device table: partially fill DTE table (Cloudflare makes me anxious so save early...)
• 20:4720:47, 20 February 2026 diff hist +5‎ AMD-Vi IOMMU ‎ →‎Commands: explicitly note head/tail is reset to 0
• 20:4520:45, 20 February 2026 diff hist +181‎ X86 Paging ‎ →‎Page Map Table Entries: Note about AVL bits and IOMMU
• 20:4020:40, 20 February 2026 diff hist +460‎ AMD-Vi IOMMU ‎ I/O page tables: PTE / PDE tables
• 19:5819:58, 20 February 2026 diff hist −21‎ AMD-Vi IOMMU ‎ →‎MMIO: fix typo'd offset for SMI Filter Register 14
• 19:5719:57, 20 February 2026 diff hist 0‎ User:Demindiro/AMD-Vi IOMMU article scratchpad ‎ →‎amd-iommu-registers.txt: fix typo'd offset for SMI Filter Register 14 current
• 19:5519:55, 20 February 2026 diff hist +5,007‎ N User:Demindiro/AMD-Vi IOMMU article scratchpad ‎ Created page with "Tip for X11 users: <code>xclip</code> + middle mouse button :) <syntaxhighlight lang="sh"> python3 amd-iommu-registers.py | xclip </syntaxhighlight> == Table script == === <code>amd-iommu-registers.txt</code> === Format is <code>offset size name*</code>. <syntaxhighlight> 0x0030 8 IOMMU Extended Feature Register 0x0038 8 PPR Log Base Address Register 0x0040 8 IOMMU Hardware Event Upper Register 0x0048 8 IOMMU Hardware Event Lower Register 0x0050 8 Hardware Event Sta..."
• 19:5119:51, 20 February 2026 diff hist +168‎ AMD-Vi IOMMU ‎ →‎MMIO: Make table more compact, this time using a script for the entire process (will publish on my user page)
• 18:0018:00, 20 February 2026 diff hist 0‎ AMD-Vi IOMMU ‎ →‎Commands: swapped head and tail roles
• 16:5516:55, 20 February 2026 diff hist 0‎ AMD-Vi IOMMU ‎ →‎Commands
• 16:4116:41, 20 February 2026 diff hist +27‎ AMD-Vi IOMMU ‎ →‎Commands: manual reset of head/tail is not necessary (and QEMU doesn't like it anyway)
• 15:3915:39, 20 February 2026 diff hist 0‎ AMD-Vi IOMMU ‎ →‎Commands: Put length encoding table below base register table
• 15:3815:38, 20 February 2026 diff hist +259‎ AMD-Vi IOMMU ‎ →‎Commands: Length table
• 15:3415:34, 20 February 2026 diff hist +1,833‎ AMD-Vi IOMMU ‎ →‎Commands
• 14:5614:56, 20 February 2026 diff hist +295‎ AMD-Vi IOMMU ‎ →‎Registers: note about MMIO access sizes, per documentation

19 February 2026

• 19:4419:44, 19 February 2026 diff hist +4‎ m ARM SMMU versions 1 and 2 ‎ Link to (non-existent) IOMMU page. Ideally someone with broad knowledge about IOMMUs should write the IOMMU page.
• 19:4019:40, 19 February 2026 diff hist 0‎ AMD-Vi IOMMU ‎ →‎MMIO: properly mark 0x2098 to 0x2FFC as reserved
• 19:3919:39, 19 February 2026 diff hist +26‎ N User:Demindiro/AMD-Vi IOMMU ‎ Demindiro moved page User:Demindiro/AMD-Vi IOMMU to AMD-Vi IOMMU: Unfinished but I want to make sure it is searchable. I will continue working on it. current Tag: New redirect
• 19:3919:39, 19 February 2026 diff hist 0‎ m AMD-Vi IOMMU ‎ Demindiro moved page User:Demindiro/AMD-Vi IOMMU to AMD-Vi IOMMU: Unfinished but I want to make sure it is searchable. I will continue working on it.
• 19:3619:36, 19 February 2026 diff hist +471‎ AMD-Vi IOMMU ‎ Events stub
• 19:3219:32, 19 February 2026 diff hist +344‎ AMD-Vi IOMMU ‎ Command stubs
• 19:2719:27, 19 February 2026 diff hist +1,001‎ AMD-Vi IOMMU ‎ →‎MMIO: 0x2000 to 0x3000
• 19:2219:22, 19 February 2026 diff hist +466‎ AMD-Vi IOMMU ‎ →‎MMIO: autogenerate rows 0x2000 to 0x2090 (blank)
• 19:1619:16, 19 February 2026 diff hist +243‎ AMD-Vi IOMMU ‎ →‎MMIO: 0x1000-0x2000
• 19:1019:10, 19 February 2026 diff hist +3,641‎ AMD-Vi IOMMU ‎ →‎Registers: MMIO 0x0000 to 0x1000 (mixing 32-bit registers in with 64-bits has to be an elaborate troll)
• 18:3618:36, 19 February 2026 diff hist +365‎ AMD-Vi IOMMU ‎ PCI base capability registers table
• 18:1318:13, 19 February 2026 diff hist +1,659‎ N AMD-Vi IOMMU ‎ Created page with "{{stub}} AMD-Vi provides a IOMMU to translate "Device Virtual Addresses" (DVAs) to "System Physical Addresses" (SPAs). Without nested paging, it is equivalent to translating linear/virtual addresses to physical addresses. It is also able to remap interrupt lines. The IOMMU can be located in the PCI configuration space and is identified by checking class=0x8, subclass=0x6 and progif=0x0. None of the BAR registers are used, instead registers in capability space (id=0..."

10 January 2026

• 19:1319:13, 10 January 2026 diff hist +33‎ N ExoOs ‎ Demindiro moved page ExoOs to User:Exoosdev/ExoOs: Please use the project list current Tag: New redirect
• 19:1319:13, 10 January 2026 diff hist 0‎ m User:Exoosdev/ExoOs ‎ Demindiro moved page ExoOs to User:Exoosdev/ExoOs: Please use the project list

9 January 2026

• 16:2216:22, 9 January 2026 diff hist −19‎ CRC32 ‎ →‎Without table: use jrcxz