TSC
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Introduction
The Timestamp Counter is a 64-bit internal register which is present in all Intel processors after the Pentium. It stores the number of cycles executed by the CPU after the latest reset. The time-stamp counter can be read by software using the RDTSC instruction. It was a precise method of getting a high-resolution measure of the passage of time. But on hyper-threading and multi-core systems, user-level software cannot rely on it as the time-stamp counters of all the CPUs in the system may or may not be synchronized. Other than that, the speed of the CPU may change as the OS or BIOS may take power-saving steps or step-up the performance of the CPU using hardware-based mechanisms. But recent processors also allow a constant-rate TSC which ticks at the nominal frequency of the CPU rather than the current-frequency of the CPU which depends on a turbo state or power-saving state. This feature is used in kernels to record time with high-precision and low-overhead on each CPU.
Portability
The TSC and related instructions are not portable and using them in user-level software is not advised due to portability reasons. Some CPU vendors which compete with Intel don't have a TSC or don't implement the RDTSC instruction.
Relation with the APIC Timer
The TSC is now used widely for measuring time in modern kernels, like the linux kernel. The APIC timer can be set to the TSC-deadline mode which uses the processor's internal time-stamp counter to issue an interrupt when the counter exceeds a specific value decided by software. But it is not guaranteed that the APIC timer will use the processor's core crystal frequency (internal clock) or the processor's bus clock. The IA32_TSC_DEADLINE_MSR (model-specific register) is used for setting the deadline value when the interrupt should be issued.
