Talk:PCI IDE Controller

We already have a complete set of articles on ATA PIO Mode, ATAPI, SATA, and ATA DMA programming. Most of the programming information here is redundant, and is not as good as in the other articles.
Bewing 01:18, 9 November 2009 (UTC)

• Though true, I think the tutorial here is very useful. The other articles are pretty cryptic IMHO, so I certainly don't think we should throw this article away. Creature 16:06, 10 November 2009 (GMT + 1)

• If the article is to remain, it will have to be proof read.. spelling errors and other grammatical issues make it difficult to follow the authors code-commentary. --Brynet-Inc 16:39, 10 November 2009 (UTC)

• • I'm trying to work my way through the article, but could use some help. I'm currently grammar checking the article and getting rid of obvious errors --Computafreak 22:06, 10 November 2009 (UTC)

• The article says that a PATA hard drive will use IRQs 14 and 15. Isn't it instead that the master uses 14 and the slave 15 (or vice versa)? Alethiophile 00:44, 17 August 2010 (UTC)

• • No, it goes by bus. Both drives on bus #0 (the primary bus) use IRQ14, and both drives on bus #1 (secondary) use IRQ15.
    Bewing 04:32, 19 August 2010 (UTC)

• According to the ATA PIO Mode page, LBA Bytes 4, 5 and 6 use the same ports as LBA 1, 2 and 3 respectively. They are just sent before the lower order values. This article states that 4, 5 and 6 get their own ports. Can we verify which is correct? --Spydertl2 02:14, 5 October 2010 (UTC)

• • I think I've figured it out. Later in the article, it clarifies the low/high byte issue with the ports. I was looking at the register list, which differentiates between ports and "registers". These enumerated "register" values are apparently converted to port numbers in code. This should probably be explicitly noted in the article that these values are NOT port offsets. :) --Spydertl2

• This article appears to have plenty of information relating to IDE ports on PCI buses in particular. Also it is the only place I could find where the individual IDE IO port registers are individually listed. This page may repeat some things but it is not superfluous. --Michaelslade 14:55, 29 January 2011 (UTC)

• Source to the Hale Landis driver is easier found through archive.org mindrvr.zip Neozeed 19:32, 18 April 2018 (CDT)

Registry trashing

It should be noted that, this line:
asm("pushw %es; movw %ds, %ax; movw %ax, %es;");

Will trash the ax register, it should probably be replaced with:
asm("pushw %es; pushw %ax; movw %ds, %ax; movw %ax, %es; popw %ax;"); --Tobba 17:26, 6 June 2011 (UTC)

Irrelevent. [[r]e]ax is the general purpose register. The next thing that will happen is that a value off the stack will be stuck in ax so the if statement can be evaluated. (Yes I know that any optimising compiler will probably use a different one, but an optimising compiler will be able to work out that ax is trashed and work around that) Andyhhp 22:58, 6 June 2011 (UTC)

GCC for one doesn't: it can't interpret anything within asm blocks (do you really think they have a full blown assembly interpreter for each architecture) and must rely on its specification to find out what it does. It may discard the asm block, it may assume that ax is unmodified, but even worse, it will assume that esp is unmodified(!). This page has been disputed for a reason. - Combuster 09:50, 8 June 2011 (UTC)

Non-standard outb argument order

It should be noted, if someone decides to fix this article (it would be usefull if it was corrected), that the arguments to outb is in the wrong order, assuming the reader use the "standard" outb function from here: http://wiki.osdev.org/Inline_Assembly/Examples

PCI BAR detection

The BAR detection here is (for the base register)

(BAR0&0xFFFFFFFC) + 0x1F0*(!BAR0)

Is this really correct? It works with an IDE controller, but not a SATA in my IDE driver (based on this tutorial). Plus, the values on MS calc after these operations are completely wrong. Not'ing the final answer and adding 1 seems the only way to get near correct.

There is another problem with PCI BARs in this article. IO port BARs are 4-byte aligned and the first two bits are always "01". The ide_initialize routine does not take this into account and uses misaligned ATA control ports (0x3F6, 0x376).

Tree5678 10:10, 7 May 2022 (CDT)

Control Offset Incorrect

The Control Register offset in the article code examples appears to be wrong. It suggests the Control Register is at offset 2 from the control base (0x0C-0x0A), but it's actually at offset 0. This code:

else if (reg < 0x0E)
  outb(channels[channel].ctrl  + reg - 0x0A, data);

should be changed to:

else if (reg < 0x0E)
  outb(channels[channel].ctrl  + reg - 0x0C, data);

Giawa 10:26, 29 December 2021 (CST)