Intel Architecture 64 bit. The first document describing the new instruction set was published by Intel in May 1999. The name IA64 was published beforehand, and some of the features were known beforehand (predication and wide-issue were discussed in December 1997 on comp.arch). Itanium processors natively supported the x86 instruction sets, but they stripped the x86 hardware emulation feature from the processor due to its bad performance. The latest Itanium processors emulate the x86 instructions with software emulation techniques (binary emulation, binary translation).
IA64 is a completely different instruction set from the more familiar x86 (and should not be confused with x86-64 - which is very much like x86). Intel promised that IA64 implementations would natively execute x86 code (including operating systems).
- 128 bit wide instruction bundles, containing 2 or 3 instructions, along with a template (which describes the instruction types and dependency information)
- "register stack engine" which would automatically store some registers to memory on function calls (and load them back on return)
- extremely large (128 count) register files
- several features intended to expose out-of-order processing to the compiler
- explicit loop branches, with rotating registers (for software pipelining)
- non-faulting loads
- loads which check against later stores
- 3 or 4 register, non-destructive format (dest = src1 op src2; dest = src1 * src2 + src3)
- each instruction is predicated (conditionally executed based on a 1-bit register)
- simple addressing modes (register indirect, with post increment)
- Merced (released as Itanium, not to be confused with the Itanium Instruction Set aka IA-64)
- McKinley (released as Itanium 2)