From OSDev Wiki
Jump to: navigation, search

This article is a stub! This page or section is a stub. You can help the wiki by accurately contributing to it.

Warning: Many parts of RISC-V are not yet finally. Things might and will change! Look at the official specification for the most up-to-date information

RISC-V is not a single ISA, rather a meta-ISA. It defines basics and boundaries for a family of implementations. The specification is published under a Creative Common License and actively developed on github. The problems, which are addressed by developement of RISC-V are the legal problems with developing real (hardware) processors, be it for educational, hobbyist or economical purposes of most other architectures and the huge historical baggage of some processor families (x86...). An implementation consists of one of the Base ISAs and zero or more Extensions.



The RISC-V ISA has fixed-length 32-bit instructions aligned on their natural boundaries, but is designed to encode variable-length instructions.
The base ISA operates on a little-endian memory system, but non-standard extensions may add support for big-endian or bi-endian.

Hardware Threads

The RISC-V ISA specifies hardware threads, called harts. A hart is defined by its own instruction fetch unit. A processor may contain multiple harts, at least one. Each hart has an ID associated with it.

Exceptions, Traps and Interrupts

In RISC-V the term Exception refers to an unusual condition at run-time associated with an instruction in the current hardware thread.
A Trap is a synchronous transfer of control to a trap handler and is caused by an exceptional condition within a RISC-V thread. The trap handlers usually execute in a more privileged environment.
An external event that occurs asynchronously to the current thread will cause an Interrupt. When an interrupt occurs, some instruction is selected to experience a trap.


The spec defines 4 priviledge modes, of which a valid combination has to be implemented. The modes are:

Debug Mode for complete control, for debuggers
Machine Mode with nearly full control, no debug registers (think firmware), not optional
Hypervisor VM-Hypervisor
Supervisor OS-level
User Application-level, lowest privilege

Possible Combinations

Valid combinations of privilege levels are:

  • One level: Machine mode only for embedded systems
  • Two levels: Machine and User mode, small systems
  • Three levels: Machine, Supervisor and User mode, Complex systems able to run Unix-like operating systems

Base ISA

The base ISA specifies RV32I and RV64I, 32 and 64-bit respectively, most of what is said about RV32I also applies to RV64I. Additionally, there is also RV32E, a reduced version of RV32I for embedded systems and RV128I, a 128-bit version, which is mostly a placeholder so far.


RV32I offers 31 general-purpose registers (x1-x31) which hold integer values, the x0 register is hardwired to zero, all registers are 32 bits wide. It specifies a number of logical and arithmetic operations (and, or, xor, shift left and right, addition and subtraction), all of which are available with a source register or an immediate.


RV32E reduces the number of general-purpose registers to 15 (x1-x15), and x0 is still hardwired to constant zero.


RV64I is very similar to its 32-bit counterpart, but offers 64-bit wide registers and can read the CSRs in one operation instead of requiring the programmer to read the upper and lower half separately. Additionaly, there are some instructions to work with words (32 bit) instead of double-words.


Like RV64I but 128bit register length.


An extensions can be one of the officialy defined ones or a vendor-specific one (there is opcode space explicitely reserved for this) and can define additional elements, including opcodes and registers.

The following Standard Extensions are noteworthy here:


This extensions defines some kind of secondary address space for Control and Status Register, which are used for controlling thins like interrupts, privilege level, hart-local timers and such. These registers can be accessed via the CSR instructions.

RVM (Multiply-Divide Instruction Extension)

The RVM Extension adds instructions for multiplying, dividing and computing the remainder of a division.

RVA (Atomic Instruction Extension)

The RVA Extension adds instruction to work atomically with memory, including reserved load and conditional store.

RVF & RVD & RVQ (Floating Point Extensions)

Adds additional instructions to work with floating points and also the floating point registers. The different extensions differ in the length|precision of the floating point numbers.

C (Compressed Instructions Extension)

Allows 16-bit variants of common instructions with a reduced register set (16 instead of 32) and is intented to increase code density. It can be freely mixed with 32-bit instructions

Running RISC-V

Emulator, Simulators, etc

For advanced setups (multiple privilege modes etc) QEMU is probably the way to go. Other simulators exist, but the author has not yet tried them :-)

Real Hardware

There does not exist that much real RISC-V hardware. The most notable example would probably be the HiFive Unleashed, which is able to run linux, has multiple cores and is expandable.

The PolarFire SoC Icicle Kit [1] by Microchip also contains cores by sifive and can run linux, but is cheaper than the HiFive Unleashed.

Most other hardware implementations (which are for sale for normal consumers) are more in the category of "microcontrollers" and lacks parts like a Memory Management Unit (MMU), I/O for humans (keyboard, graphics, sound, etc).

The Kendryte K210 (e.g. in the MAIX Bit-board) is a RV64IMACFD_Zicsr_Zifence processor with two harts and quite cheap.

See Also

External Links

Personal tools