The RISC-V ISA has fixed-length 32-bit instructions aligned on their natural boundaries, but is designed to encode variable-length instructions.
The base ISA operates on a little-endian memory system, but non-standard extensions may add support for big-endian or bi-endian.
The RISC-V ISA specifies hardware threads, also known as harts, that allow the processor to execute multiple independent streams of instructions. It is up to the processor to decide how to schedule these threads and among which of it's cores. Each hart has an ID associated with it
Exceptions, Traps and Interrupts
In RISC-V the term Exception refers to an unusual condition at run-time associated with an instruction in the current hardware thread.
A Trap is a synchronous transfer of control to a trap handler and is caused by an exceptional condition within a RISC-V thread. The trap handlers usually execute in a more privileged environment.
An external event that occurs asynchronously to the current thread will cause an Interrupt. When an interrupt occurs, some instruction is selected to experience a trap.
The base ISA specifies RV32I and RV64I, 32 and 64-bit respectively, most of what is said about RV32I also applies to RV64I. Additionally, there is also RV32E for embedded systems.
RV32I offers 31 general-purpose registers (x1-x31) which hold integer values, the x0 register is hardwired to zero, all registers are 32 bits wide. It specifies a number of logical and arithmetic operations (and, or, xor, shift left and right, addition and subtraction), all of which are available with a source register or an immediate.
RV32E reduces the number of general-purpose registers to 15 (x1-x15), and x0 is still hardwired to constant zero.
RV64I is very similar to its 32-bit counterpart, but offers 64-bit wide registers and can read the CSRs in one operation instead of requiring the programmer to read the upper and lower half separately.