User:Gravaera/ARMv8 Overview

This page seeks to provide a reference which will be a refresher for an individual who has previously already read the ARMv8 manuals. It neither claims nor seeks to be an exhaustive overview of ARMv8.

ARMv8 abstract machine

An ARMv8 implementation's abstract virtual machine consists of:

• Execution state:
• ISA mode.
• System Registers.
• Debug Architecture v8.

Execution state

Execution state encompasses the supported register set, the supported ISAs, portions of the exception model, the VMSA state and the programmers' model. There are two broad execution state choices:

ARMv8 supports transitioning between execution states (AArch32 and AArch64) but only by transitioning from one Exception Level to another. This support enables an AArch64 supervisor/hypervisor to support a subordinate software layer running in a different exception level, in a different execution state. ARM calls such transitions between execution states "**Interprocessing**".

AArch64 execution state:

• 31 64-bit GP regs, including X30 which takes on the role of the traditional LR register (link register); a 64-bit PC, SP and ELR (Exception Link Register).
• 32 128-bit SIMD registers for vector and scalar FP.
• Only one ISA: The A64 ISA.
• ARMv8 Exception Model with up to 4 exception levels: EL0-EL3 that form the execution privilege lobster hierarchy.
• VMSAv8 implementation which provides up to 64 bit virtual addressing.
• PSTATE elements which contain PE state, and A64 instructions which manipulate PSTATE.
• Intuitive naming scheme for system registers which a suffix that indicates the lowest EL at which the register is accessible.

AArch32 execution state:

• 12 32-bit GP regs, 32-bit PC, LR and SP. In AArch32 the LR is used both as ELR and the procedure link register.
• Banked register state which is accessible in different PE modes.
• A single ELR_Hyp register for returns from Hyp mode.
• 32 64-bit registers for SIMD vector and scalar FP.
• Support for 2 ISAs (A32 and T32).
• ARMv7-a exception model with enhancements to map it onto the ARMv8 Exception Model (based on Exception Levels).
• VMSAv7 which supports up to 32 bits of virtual addressing.
• PSTATE elements. A32 and T32 ISAs have instructions which can manipulate PSTATE.

ISA Mode

• A64 uses 64bit registers, but a fixed 32-bit instruction encoding.
• A32 uses 32-bit registers and a fixed 32-bit instruction encoding.
• T32 uses a variable length instruction encoding which can either be 16 or 32-bits long.

Profiles (Sec A1.2)

• A-profile supports the A32, T32 and A64 instruction sets.
• R-profile supports only the A32 and T32 ISAs.
• M-profile supports only the a variant of the T32 ISA.

By implication, R and M profile PEs do not support execution in AArch64 mode and M profile PEs only support execution in Thumb mode.

Debug Architecture

A1.2.1 "The ARM Debug architecture is fully integrated with the architecture, and does not have a separate version number." A1.3.4: "All ARMv8 implementations support both models [Self-hosted Debug and External debug]." I.e, it appears that ARMv8 Debug is meant to be supported by all implementations.