User:Gravaera/RISC-V Virtualization

Virtualization: ENABLE BITS FOR VIRTUALIZATION: MMU Management trapping (enable with MSTATUS.TVM): * Hardwired to 0 (disabled) if SMode unsupported (MISA.Extensions[S]=0). * Traps all accesses to SATP CSR. * Traps all executions of SFENCE.VMA instr by SMode.

WFI trapping (enable with MSTATUS.TW): * Hardwired to 0 (disabled) if SMode unsupported. * Traps execution of WFI by SMode (not by UMode). * After WFI is executed, an IMPLEMENTATION DEFINED countdown is done and if CPU is still halted, trap is taken to MMode.

SRET instr trapping (enable with MSTATUS.TSR): * This is provided to enable simulation of something called "Augmented Virtualization".

Injecting external IRQs into SMode/UMode from MMode: * See mip.[SEIP/UEIP] bit. ^ This bit has unusual behaviour in that reading it in certain ways will return a value OR'd with a value from the chipset's PIC. ^ Writing this bit with a CSRR[SC] RMW instr will always ONLY write the mip.[xEIP] bit tho. ^ mip.[UEIP] is only accessible if misa.Ext[N]==1 (UMode interrupts). * mip.[UEIP] works the same way as mip.[SEIP].